/********************************************************************************
  * @Copyright: Metanergy Technology R&D Co., Ltd
  * @Filename: myg0025_dma.h
  * @brief: DMA init and functions configure
  * @Author: AE Team
  *******************************************************************************/

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MYG0025_DMA_H
#define __MYG0025_DMA_H

#ifdef __cplusplus
extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "myg0025.h"

/** @addtogroup DMA
  * @{
  */


/* Exported types ------------------------------------------------------------*/
/** @defgroup DMA_Exported_Types DMA_Exported_Types
  * @{
  */

/**
  * @brief  DMA Init structures definition
  */
typedef struct
{
    uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMA Channelx.              */

    uint32_t DMA_MemoryBaseAddr;     /*!< Specifies the memory base address for DMA Channelx.                  */

    uint32_t DMA_DIR;                /*!< Specifies if the peripheral is the source or destination.
                                        This parameter can be a value of @ref DMA_data_transfer_direction     */

    uint32_t DMA_BufferSize;         /*!< Specifies the buffer size, in data unit, of the specified Channel.
                                        The data unit is equal to the configuration set in DMA_PeripheralDataSize
                                        or DMA_MemoryDataSize members depending in the transfer direction     */

    uint32_t DMA_PeripheralInc;      /*!< Specifies whether the Peripheral address register is incremented or not.
                                        This parameter can be a value of @ref DMA_peripheral_incremented_mode */

    uint32_t DMA_MemoryInc;          /*!< Specifies whether the memory address register is incremented or not.
                                        This parameter can be a value of @ref DMA_memory_incremented_mode     */

    uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
                                        This parameter can be a value of @ref DMA_peripheral_data_size        */

    uint32_t DMA_MemoryDataSize;     /*!< Specifies the Memory data width.
                                        This parameter can be a value of @ref DMA_memory_data_size            */

    uint32_t DMA_Mode;               /*!< Specifies the operation mode of the DMA Channelx.
                                        This parameter can be a value of @ref DMA_circular_normal_mode
                                        @note: The circular buffer mode cannot be used if the memory-to-memory
                                              data transfer is configured on the selected Channel */

    uint32_t DMA_Priority;           /*!< Specifies the software priority for the DMA Channelx.
                                        This parameter can be a value of @ref DMA_priority_level              */

    uint32_t DMA_M2M;                /*!< Specifies if the DMA Channelx will be used in memory-to-memory transfer.
                                        This parameter can be a value of @ref DMA_memory_to_memory            */

    uint32_t DMA_Request_Source;     /* set the Request Source of DMAx channely .
                                        This parameter can be a value of @ref DMA_Request_Source             */

} DMA_InitTypeDef;

/**
  * @}
  */

/* Exported constants --------------------------------------------------------*/

/** @defgroup DMA_Exported_Constants DMA_Exported_Constants
  * @{
  */
#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA_Channel1) || \
                                   ((PERIPH) == DMA_Channel2) || \
                                   ((PERIPH) == DMA_Channel3) || \
                                   ((PERIPH) == DMA_Channel4) || \
                                   ((PERIPH) == DMA_Channel5))


/** @defgroup DMA_data_transfer_direction DMA_data_transfer_direction
  * @{
  */

#define DMA_DIR_PeripheralSRC              ((uint32_t)0x00000000)
#define DMA_DIR_PeripheralDST              DMA_CCR_DIR

#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \
                         ((DIR) == DMA_DIR_PeripheralDST))
/**
  * @}
  */

/** @defgroup DMA_peripheral_incremented_mode DMA_peripheral_incremented_mode
  * @{
  */

#define DMA_PeripheralInc_Disable          ((uint32_t)0x00000000)
#define DMA_PeripheralInc_Enable           DMA_CCR_PINC

#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \
                                            ((STATE) == DMA_PeripheralInc_Enable))
/**
  * @}
  */

/** @defgroup DMA_memory_incremented_mode DMA_memory_incremented_mode
  * @{
  */

#define DMA_MemoryInc_Disable              ((uint32_t)0x00000000)
#define DMA_MemoryInc_Enable               DMA_CCR_MINC

#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \
                                        ((STATE) == DMA_MemoryInc_Enable))
/**
  * @}
  */

/** @defgroup DMA_peripheral_data_size DMA_peripheral_data_size
  * @{
  */

#define DMA_PeripheralDataSize_Byte        ((uint32_t)0x00000000)
#define DMA_PeripheralDataSize_HalfWord    DMA_CCR_PSIZE_0
#define DMA_PeripheralDataSize_Word        DMA_CCR_PSIZE_1

#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
                                           ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
                                           ((SIZE) == DMA_PeripheralDataSize_Word))
/**
  * @}
  */

/** @defgroup DMA_memory_data_size DMA_memory_data_size
  * @{
  */

#define DMA_MemoryDataSize_Byte            ((uint32_t)0x00000000)
#define DMA_MemoryDataSize_HalfWord        DMA_CCR_MSIZE_0
#define DMA_MemoryDataSize_Word            DMA_CCR_MSIZE_1

#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
                                       ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
                                       ((SIZE) == DMA_MemoryDataSize_Word))
/**
  * @}
  */

/** @defgroup DMA_circular_normal_mode DMA_circular_normal_mode
  * @{
  */

#define DMA_Mode_Normal                    ((uint32_t)0x00000000)
#define DMA_Mode_Circular                  DMA_CCR_CIRC

#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular))
/**
  * @}
  */

/** @defgroup DMA_priority_level DMA_priority_level
  * @{
  */

#define DMA_Priority_VeryHigh              DMA_CCR_PL
#define DMA_Priority_High                  DMA_CCR_PL_1
#define DMA_Priority_Medium                DMA_CCR_PL_0
#define DMA_Priority_Low                   ((uint32_t)0x00000000)

#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
                                   ((PRIORITY) == DMA_Priority_High) || \
                                   ((PRIORITY) == DMA_Priority_Medium) || \
                                   ((PRIORITY) == DMA_Priority_Low))
/**
  * @}
  */

/** @defgroup DMA_memory_to_memory DMA_memory_to_memory
  * @{
  */

#define DMA_M2M_Disable                    ((uint32_t)0x00000000)
#define DMA_M2M_Enable                     DMA_CCR_MEM2MEM

#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable))


/**
  * @}
  */

/** @defgroup DMA_Request_Source DMA_Request_Source
  * @{
  */

#define DMA_REQ_MEM_MEM                 ((uint32_t)0x00000000)
#define DMA_REQ_ADC_QUE0                ((uint32_t)0x00000000)
#define DMA_REQ_ADC_QUE1                ((uint32_t)0x00000001)
#define DMA_REQ_ADC_QUE2                ((uint32_t)0x00000002)
#define DMA_REQ_ADC_QUE3                ((uint32_t)0x00000003)
#define DMA_REQ_ADC_COM                 ((uint32_t)0x00000004)
#define DMA_REQ_SPI1_RX                 ((uint32_t)0x00000005)
#define DMA_REQ_SPI1_TX                 ((uint32_t)0x00000006)
#define DMA_REQ_UART1_RX                ((uint32_t)0x00000007)
#define DMA_REQ_UART1_TX                ((uint32_t)0x00000008)
#define DMA_REQ_UART2_RX                ((uint32_t)0x00000009)
#define DMA_REQ_UART2_TX                ((uint32_t)0x0000000A)
#define DMA_REQ_I2C1_TX                 ((uint32_t)0x0000000B)
#define DMA_REQ_I2C1_RX                 ((uint32_t)0x0000000C)
#define DMA_REQ_TIM1_CH1                ((uint32_t)0x0000000D)
#define DMA_REQ_TIM1_CH2                ((uint32_t)0x0000000E)
#define DMA_REQ_TIM1_CH3                ((uint32_t)0x0000000F)
#define DMA_REQ_TIM1_CH4                ((uint32_t)0x00000010)
#define DMA_REQ_TIM1_UP                 ((uint32_t)0x00000011)
#define DMA_REQ_TIM1_TRIG               ((uint32_t)0x00000012)
#define DMA_REQ_TIM1_COM                ((uint32_t)0x00000013)
#define DMA_REQ_TIM2_CH1                ((uint32_t)0x00000014)
#define DMA_REQ_TIM2_CH2                ((uint32_t)0x00000015)
#define DMA_REQ_TIM2_CH3                ((uint32_t)0x00000016)
#define DMA_REQ_TIM2_CH4                ((uint32_t)0x00000017)
#define DMA_REQ_TIM2_UP                 ((uint32_t)0x00000018)
#define DMA_REQ_TIM2_TRIG               ((uint32_t)0x00000019)
#define DMA_REQ_TIM3_CH1                ((uint32_t)0x0000001A)
#define DMA_REQ_TIM3_CH2                ((uint32_t)0x0000001B)
#define DMA_REQ_TIM3_CH3                ((uint32_t)0x0000001C)
#define DMA_REQ_TIM3_CH4                ((uint32_t)0x0000001D)
#define DMA_REQ_TIM3_UP                 ((uint32_t)0x0000001E)
#define DMA_REQ_TIM3_TRIG               ((uint32_t)0x0000001F)

#define IS_DMA_REQ_SRC(SRC)               (((SRC) == DMA_REQ_ADC_QUE0) || ((SRC) == DMA_REQ_ADC_QUE1)||\
                                            ((SRC) == DMA_REQ_ADC_QUE2) || ((SRC) == DMA_REQ_ADC_QUE3)||\
                                            ((SRC) == DMA_REQ_ADC_COM) || ((SRC) == DMA_REQ_SPI1_RX)||\
                                            ((SRC) == DMA_REQ_SPI1_TX) || ((SRC) == DMA_REQ_UART1_RX)||\
                                            ((SRC) == DMA_REQ_UART1_TX) || ((SRC) == DMA_REQ_UART2_RX)||\
                                            ((SRC) == DMA_REQ_UART2_TX) || ((SRC) == DMA_REQ_I2C1_TX)||\
                                            ((SRC) == DMA_REQ_I2C1_RX) || ((SRC) == DMA_REQ_TIM1_CH1)||\
                                            ((SRC) == DMA_REQ_TIM1_CH2) || ((SRC) == DMA_REQ_TIM1_CH3)||\
                                                                  ((SRC) == DMA_REQ_TIM1_CH4) || ((SRC) == DMA_REQ_TIM1_UP)||\
                                            ((SRC) == DMA_REQ_TIM1_TRIG) || ((SRC) == DMA_REQ_TIM1_COM)||\
                                            ((SRC) == DMA_REQ_TIM2_CH1) || ((SRC) == DMA_REQ_TIM2_CH2)||\
                                            ((SRC) == DMA_REQ_TIM2_CH3) || ((SRC) == DMA_REQ_TIM2_CH4)||\
                                            ((SRC) == DMA_REQ_TIM2_UP) || ((SRC) == DMA_REQ_TIM2_TRIG)||\
                                            ((SRC) == DMA_REQ_TIM3_CH1) || ((SRC) == DMA_REQ_TIM3_CH2)||\
                                            ((SRC) == DMA_REQ_TIM3_CH3) || ((SRC) == DMA_REQ_TIM3_CH4)||\
                                            ((SRC) == DMA_REQ_TIM3_UP) || ((SRC) == DMA_REQ_TIM3_TRIG))


/**
  * @}
  */


/** @defgroup DMA_interrupts_definition DMA_interrupts_definition
  * @{
  */

#define DMA_IT_TC                          DMA_CCR_TCIE
#define DMA_IT_HT                          DMA_CCR_HTIE
#define DMA_IT_TE                          DMA_CCR_TEIE

#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))

#define DMA_IT_GL1                        (DMA_ISR_GIF  + (uint32_t)0x00000000)
#define DMA_IT_TC1                        (DMA_ISR_TCIF + (uint32_t)0x00000000)
#define DMA_IT_HT1                        (DMA_ISR_HTIF + (uint32_t)0x00000000)
#define DMA_IT_TE1                        (DMA_ISR_TEIF + (uint32_t)0x00000000)
#define DMA_IT_GL2                        (DMA_ISR_GIF  + (uint32_t)0x01000000)
#define DMA_IT_TC2                        (DMA_ISR_TCIF + (uint32_t)0x01000000)
#define DMA_IT_HT2                        (DMA_ISR_HTIF + (uint32_t)0x01000000)
#define DMA_IT_TE2                        (DMA_ISR_TEIF + (uint32_t)0x01000000)
#define DMA_IT_GL3                        (DMA_ISR_GIF  + (uint32_t)0x02000000)
#define DMA_IT_TC3                        (DMA_ISR_TCIF + (uint32_t)0x02000000)
#define DMA_IT_HT3                        (DMA_ISR_HTIF + (uint32_t)0x02000000)
#define DMA_IT_TE3                        (DMA_ISR_TEIF + (uint32_t)0x02000000)
#define DMA_IT_GL4                        (DMA_ISR_GIF  + (uint32_t)0x03000000)
#define DMA_IT_TC4                        (DMA_ISR_TCIF + (uint32_t)0x03000000)
#define DMA_IT_HT4                        (DMA_ISR_HTIF + (uint32_t)0x03000000)
#define DMA_IT_TE4                        (DMA_ISR_TEIF + (uint32_t)0x03000000)
#define DMA_IT_GL5                        (DMA_ISR_GIF  + (uint32_t)0x04000000)
#define DMA_IT_TC5                        (DMA_ISR_TCIF + (uint32_t)0x04000000)
#define DMA_IT_HT5                        (DMA_ISR_HTIF + (uint32_t)0x04000000)
#define DMA_IT_TE5                        (DMA_ISR_TEIF + (uint32_t)0x04000000)

#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0FFFFF0) == 0x00) || (((IT) & 0xE0FFFFF0) == 0x00)) && ((IT) != 0x00))

#define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_GL1) || ((IT) == DMA_IT_TC1) || \
                           ((IT) == DMA_IT_HT1) || ((IT) == DMA_IT_TE1) || \
                           ((IT) == DMA_IT_GL2) || ((IT) == DMA_IT_TC2) || \
                           ((IT) == DMA_IT_HT2) || ((IT) == DMA_IT_TE2) || \
                           ((IT) == DMA_IT_GL3) || ((IT) == DMA_IT_TC3) || \
                           ((IT) == DMA_IT_HT3) || ((IT) == DMA_IT_TE3) || \
                           ((IT) == DMA_IT_GL4) || ((IT) == DMA_IT_TC4) || \
                           ((IT) == DMA_IT_HT4) || ((IT) == DMA_IT_TE4) || \
                                       ((IT) == DMA_IT_GL5) || ((IT) == DMA_IT_TC5) || \
                           ((IT) == DMA_IT_HT5) || ((IT) == DMA_IT_TE5))

/**
  * @}
  */

/** @defgroup DMA_flags_definition DMA_flags_definition
  * @{
  */
#define DMA_FLAG_GL1                      (DMA_ISR_GIF  + (uint32_t)0x00000000)
#define DMA_FLAG_TC1                      (DMA_ISR_TCIF + (uint32_t)0x00000000)
#define DMA_FLAG_HT1                      (DMA_ISR_HTIF + (uint32_t)0x00000000)
#define DMA_FLAG_TE1                      (DMA_ISR_TEIF + (uint32_t)0x00000000)
#define DMA_FLAG_GL2                      (DMA_ISR_GIF  + (uint32_t)0x01000000)
#define DMA_FLAG_TC2                      (DMA_ISR_TCIF + (uint32_t)0x01000000)
#define DMA_FLAG_HT2                      (DMA_ISR_HTIF + (uint32_t)0x01000000)
#define DMA_FLAG_TE2                      (DMA_ISR_TEIF + (uint32_t)0x01000000)
#define DMA_FLAG_GL3                      (DMA_ISR_GIF  + (uint32_t)0x02000000)
#define DMA_FLAG_TC3                      (DMA_ISR_TCIF + (uint32_t)0x02000000)
#define DMA_FLAG_HT3                      (DMA_ISR_HTIF + (uint32_t)0x02000000)
#define DMA_FLAG_TE3                      (DMA_ISR_TEIF + (uint32_t)0x02000000)
#define DMA_FLAG_GL4                      (DMA_ISR_GIF  + (uint32_t)0x03000000)
#define DMA_FLAG_TC4                      (DMA_ISR_TCIF + (uint32_t)0x03000000)
#define DMA_FLAG_HT4                      (DMA_ISR_HTIF + (uint32_t)0x03000000)
#define DMA_FLAG_TE4                      (DMA_ISR_TEIF + (uint32_t)0x03000000)
#define DMA_FLAG_GL5                      (DMA_ISR_GIF  + (uint32_t)0x04000000)
#define DMA_FLAG_TC5                      (DMA_ISR_TCIF + (uint32_t)0x04000000)
#define DMA_FLAG_HT5                      (DMA_ISR_HTIF + (uint32_t)0x04000000)
#define DMA_FLAG_TE5                      (DMA_ISR_TEIF + (uint32_t)0x04000000)

#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0FFFFF0) == 0x00) || (((FLAG) & 0xE0FFFFF0) == 0x00)) && ((FLAG) != 0x00))

#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_GL1) || ((FLAG) == DMA_FLAG_TC1) || \
                               ((FLAG) == DMA_FLAG_HT1) || ((FLAG) == DMA_FLAG_TE1) || \
                               ((FLAG) == DMA_FLAG_GL2) || ((FLAG) == DMA_FLAG_TC2) || \
                               ((FLAG) == DMA_FLAG_HT2) || ((FLAG) == DMA_FLAG_TE2) || \
                               ((FLAG) == DMA_FLAG_GL3) || ((FLAG) == DMA_FLAG_TC3) || \
                               ((FLAG) == DMA_FLAG_HT3) || ((FLAG) == DMA_FLAG_TE3) || \
                               ((FLAG) == DMA_FLAG_GL4) || ((FLAG) == DMA_FLAG_TC4) || \
                               ((FLAG) == DMA_FLAG_HT4) || ((FLAG) == DMA_FLAG_TE4) || \
                               ((FLAG) == DMA_FLAG_GL5) || ((FLAG) == DMA_FLAG_TC5) || \
                               ((FLAG) == DMA_FLAG_HT5) || ((FLAG) == DMA_FLAG_TE5))

/**
  * @}
  */

/** @defgroup DMA_Buffer_Size DMA_Buffer_Size
  * @{
  */

#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))

/**
  * @}
  */

/**
  * @}
  */

/** @defgroup DMA_Exported_Functions DMA_Exported_Functions
  * @{
  */

/* Function used to set the DMA configuration to the default reset state ******/
void DMA_DeInit(DMA_TypeDef *DMA_Channelx);

/* Initialization and Configuration functions *********************************/
void DMA_Init(DMA_TypeDef *DMA_Channelx, DMA_InitTypeDef *DMA_InitStruct);
void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct);
void DMA_Cmd(DMA_TypeDef *DMA_Channelx, FunctionalState NewState);

/* Data Counter functions******************************************************/
void DMA_SetCurrDataCounter(DMA_TypeDef *DMA_Channelx, uint16_t DataNumber);
uint16_t DMA_GetCurrDataCounter(DMA_TypeDef *DMA_Channelx);
void DMA_RequesrSocreConfig(DMA_TypeDef *DMA_Channelx, uint32_t DMA_CHx_Request);

/* Interrupts and flags management functions **********************************/
void DMA_ITConfig(DMA_TypeDef *DMA_Channelx, uint32_t DMA_IT, FunctionalState NewState);
FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
void DMA_ClearFlag(uint32_t DMA_FLAG);
ITStatus DMA_GetITStatus(uint32_t DMA_IT);
void DMA_ClearITPendingBit(uint32_t DMA_IT);

#ifdef __cplusplus
}
#endif

#endif /*__MYG0025_DMA_H */

/**
  * @}
  */

/**
  * @}
  */
